Abstract
The design of the All Digital FM Receiver circuit in this project uses Phase Locked Loop (PLL) as the main core. The task of the PLL is to maintain coherence between the input (modulated) signal frequency, iω and the respective output frequency, oω via phase comparison. This self-correcting ability of the system also allows the PLL to track the frequency changes of the input signal once it is locked.
Frequency modulated input signal is assumed as a series of numerical values (digital signal) via 8-bit of analog to digital conversion (ADC) circuit. The FM Receiver gets the 8 bit signal every clock cycle and outputs the demodulated signal.
In the new architecture we propose improvement of the new architecture of digital FM demodulator. This work enhances signal quality, system clock frequency, and superior than well known PLL technique today.
The All Digital FM Receiver circuit is designed using VHDL, then simulated and synthesized using Modelsim SE 6.3f simulator and Xilinx ISE 9.2i, respectively. FPGA implementation also provided, here we use Spartan 3E device.
