ABSTRACT
This paper presents a high speed, fully pipelined FPGA implementation of AES Encryption and Decryption (acronym for Advance Encryption Standard, also known as Rijndael Algorithm).The implementation of AES has been made both in sequential and pipeline architectures and we are able to compare the results as an area time trade-off. In sequential architecture, the design occupies 2744 CLB slices and achieved a throughput of 258.5 Mbits/s and there is no use of extra memory resources like FPGA BRAMs. On the other hand, our pipeline design occupies a total of 2136 CLB slices and achieved a throughput of 2868 Mbits/s. Both designs were realized on VirtexE family of devices (XCV812). The performance figures achieved by our implementations are not only efficient in terms of throughput but also area occupied by them are among the most economical reported up-to-date.
AES has a fixed block size of 128 bits and a key size of 128, 192 or 256 bits, whereas Rijndael can be specified with key and block sizes in any multiple of 32 bits, with a minimum of 128 bits and a maximum of 256 bits. AES operates on a 4×4 array of bytes, termed the state. For encryption, each round of AES (except the last round) consists of four stages. a) SubBytes - a non-linear substitution step where each byte is replaced with another according to a lookup table (known as S Box). b) ShiftRows - a transposition step where each row of the state is shifted cyclically a certain number of steps. c) MixColumns - a mixing operation which operates on the columns of the state, combining the four bytes in each column using a linear transformation. d) AddRoundKey - each byte of the state is combined with the round key; each round key is derived from the cipher key using a key schedule.
