ieee projects for ece, project for ece

Title : implementation multi channel uart using fifo


 The Multi Channel Uart Contains more than one transmit/receive per uart. All the channels can operate independently or together. Data can be received on one and transmitted on other and also the data rate on different channels can be same or different. The channels of the Multi channel uart are designed to reduce the CPU overhead when working with high speed modems and other devices. Here we are implementing a multi channel Uart which contains 4 Uarts. 
                 This multi channel uart operates in three modes one is Normal mode, second is Hub mode and last is Bridge Mode. In Normal mode all these Uarts are completely independent in functionality, but share common logic to reduce its overall size as compared to individual instantiations. In Hub mode the data received by the uart will be transmit by the other uarts. In Bridge mode the data received by the Uart1is Transmitted by the Uart2 and the data received by the Uart3 is transmitted by the Uart4. In this both the Uarts operates at different Baud rates.
             Each channel performs serial to parallel conversion on data characters received from a peripheral device, and parallel to serial conversion on data characters received from the CPU. The CPU can read the complete status of each channel at any time. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character. An optional parity bit can be attached to the data character to enhance Data integrity. The receiver checks the parity bit for any transmission bit errors. Each channel has its own baud rate value, receive and transmit FIFO and CPU registers. The user has control over the configuration of the core by modifying the parameters in the top-level source file. This allows the core to be modified and reused easily. These parameters include number of channels and FIFO depth


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